Why does `std::atomic::store` with sequential consistency use XCHG on x86?

Why does a std::atomic store with sequential consistency use XCHG?

In the context of atomic memory operations, std::atomic provides a sequential consistency guarantee for its store operation. This means that any write performed using std::atomic::store will be visible to any subsequent memory operations performed on the same location.

XCHG vs. Store with Memory Barrier

The implementation of std::atomic::store for sequential consistency typically employs an XCHG instruction on x86 and x86_64 architectures. This instruction performs an atomic exchange operation where the value stored in a memory location is replaced with a new value.

The question arises as to why XCHG is preferred over a simple store operation followed by a memory barrier. While a normal store ensures that the data is written to memory, it does not guarantee that the write will be visible to other threads or processors. A memory barrier, such as asm volatile("" ::: "memory"), forces the processor to flush any pending write buffers and synchronize memory operations across different processors.

Reasons for Using XCHG

There are several reasons why XCHG is considered a suitable choice for implementing sequential consistency in std::atomic::store:

1. Atomic Nature: XCHG is an atomic instruction, meaning that it executes as a single indivisible operation. This ensures that the write operation and the load of the previous value occur without any interleaving from other processors or threads.
2. Strong Memory Barrier: The XCHG instruction acts as a full memory barrier on x86 architectures. It forces the processor to flush its write buffer and invalidate any cached copies of the memory location. This guarantees that any changes made by the XCHG will be visible to all subsequent memory operations.
3. Performance Considerations: On certain CPUs, such as Intel Skylake, using XCHG for sequential consistency can outperform the combination of a store and a memory barrier. XCHG avoids the overhead associated with the explicit memory barrier, reducing latency and improving performance.

Alternative Approaches

While XCHG is a common implementation choice for sequential consistency in std::atomic::store, there are alternative approaches that can be used. One option is to use a MOV instruction followed by a MFENCE instruction. MOV performs a regular store operation, while MFENCE acts as a full memory barrier. This approach is used by some compilers in certain cases.

Conclusion

In summary, the use of XCHG for sequential consistency in std::atomic::store provides a reliable and efficient way to ensure that write operations are visible and ordered correctly across multiple threads and processors.

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