How Do Atomic Operations Work on x86 Processors: Cache, Memory, and Atomicity?

Atomic Operations on x86: An Internal Perspective

Unlike initial impressions that suggest memory operations are directly executed on RAM, atomic operations are confined within the cache. This coherence between cores and the use of cache-coherent DMA ensure that memory accesses appear atomic to all observers in the system.

Atomicity is notably not related to memory ordering, and aligned loads and stores up to 64 bits remain atomic regardless of ordering. This is because such operations can be executed within the wide data paths between cores, memory, and PCIe busses, ensuring indivisibility without the need for additional hardware.

The CPU guarantees atomicity for aligned loads and stores thanks to its ability to atomically modify cache lines. This allows atomic operations to occur entirely within the cache, without necessarily reaching main memory. Stores wider than the data path, however, require protection with a lock respected by all accesses.

Atomic read-modify-write (RMW) operations pose a greater challenge. To execute an RMW atomically, the core maintains a cache line in Modified state, preventing external modifications until the operation completes. For unaligned RMWs, actual DRAM storage may be necessary to enforce atomicity across multiple cache lines, potentially requiring the assertion of a bus lock.

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