How Atomic Are Double and Vector Operations on x86_64?

Atomic Operations on Doubles and Vectors in x86_64

While C 11 std::atomic offers lock-free operations on most implementations, atomic AVX or SSE vector operations remain CPU-dependent and lack assembly-level support.

Atomic Operations on Doubles

• Load and store operations are naturally atomic for 8 bytes, including doubles.
• Read-modify-write operations require a retry loop with cmpxchg (or TSX) as there is no direct memory-destination instruction.
• Cmpxchg16b is available for 16-byte atomic RMW operations.
• Some special cases of IEEE float operations can be implemented using integer operations (e.g., absolute value, negation).

Atomic Operations on Vectors

• There's no hardware support for atomic vector load/store operations across the cache-coherency system.
• Vector loads/stores on aligned arrays of doubles are likely safe to use without risking cache-line tearing.
• For 16-byte atomic load/store/RMW, cmpxchg16b can be used.
• Atomically updating 16-byte objects is possible, but reading the 8-byte halves separately is not guaranteed to be atomic.

Compiler Support

• Compilers do not always generate efficient assembly for atomic load/store (e.g., using mov instructions directly to/from xmm registers).
• Atomic vectors (atomic<__m128d> or atomic<__m256d>) are not efficiently implemented, as they require cmpxchg16b even for read-only or write-only operations.

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