How Atomic Are x86 Loads and Stores, and What Factors Affect Atomicity?

Atomicity of Loads and Stores on x86

The x86 architecture guarantees atomicity for aligned loads and stores, up to the size of the data paths between cores, memory, and I/O buses. This means that a single operation will happen indivisibly, and any other operation that observes it will see it as having occurred fully or not at all.

Internally, the CPU can implement atomicity "for free" for aligned operations because the data transfer occurs over a wide enough data bus or through a single message. For wider accesses or unaligned operations, it may need to split the operation into smaller chunks and perform more complex operations.

Atomic Operations and Cache

Atomic operations can happen entirely in the cache, as long as the operation doesn't cross a cache line boundary. This means that modifications to the cache are sufficient to ensure atomicity.

Atomic Read-Modify-Writes

Atomic read-modify-write (RMW) operations are more difficult to implement. The CPU can keep a cache line in Modified state and ignore cache coherency messages while the operation is in progress, allowing it to appear atomic to other cores.

Unaligned Locked Operations

Unaligned locked operations may require more complex hardware intervention, such as taking a bus lock to prevent other accesses during the operation.

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