How Does a Simple MOV Instruction Achieve Release-Acquire Semantics on x86?

Using MOV to Achieve Release-and-Acquire on x86: Unraveling the Mystery

The C 11 memory_order_release ensures the completion of a write to shared memory before it become visible to other threads. Similarly, memory_order_acquire guarantees that a read operation fetches the most up-to-date value written to memory.

Based on the documentation for x86, it is asserted that the MOV instruction alone conveys acquire-release semantics. However, a question arises regarding how this mechanism operates.

Exploring the X86 Memory Model

The cited Intel documentation emphasizes that reads and writes are not reordered with other similar operations on a single processor. Additionally, the multi-core section states that processors follow the same ordering principles when accessing cache-coherent shared memory.

Understanding Acquire-Release with MOV

The key to comprehending acquire-release semantics lies in recognizing that reordering occurs only locally, within each CPU core. Once a store is globally visible, it becomes accessible to all cores concurrently, and no core can perceive it before that point. Therefore, local barriers, such as mfence, ensure sequential consistency by flushing the store buffer before allowing subsequent loads.

Essentially, x86 utilizes a cache-coherent shared memory architecture, where coherent caches provide a shared view of memory across processors. The coherent nature of memory access reinforces the single-core memory model, where program order and a store buffer suffice to implement acquire-release semantics.

Broader Implications for Other ISAs

The principles of acquire-release and barrier implementation extend beyond x86. Generally, weaker memory models permit only local reordering, requiring barriers within a CPU core to enforce specific ordering.

PowerPC stands as an exception, allowing stores to become visible to some cores before others, introducing the possibility of IRIW (Independent Reads of Independent Writes) reordering. However, most hardware memory models prohibit IRIW reordering, ensuring global store ordering across all cores.

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