Known as the Intel Architecture Code Analyzer, IACA is an advanced tool for evaluating code scheduling against Intel CPUs. It operates in three modes:
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Throughput Mode: IACA gauges maximum throughput, assuming it's the body of a nested loop.
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Latency Mode: IACA pinpoints minimum latency from initial to final instructions.
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Trace Mode: IACA traces the sequence of instructions as they progress through pipelines.
Capabilities and Applications:
- Estimates scheduling for modern Intel CPUs (ranging from Nehalem to Broadwell, depending on the version).
- Reports in detailed ASCII or interactive Graphviz charts.
- Supports C, C , and x86 assembly analysis.
Usage:
Instructions for IACA usage vary depending on your programming language.
C/C :
Include the necessary IACA header (iacaMarks.h) and place start and end markers around your target loop:
1 2 3 4 5 6 7 8 | while (cond){
IACA_START
}
IACA_END
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Assembly (x86):
Insert the specified magic byte patterns to designate markers manually:
1 2 3 4 5 6 7 8 9 10 11 12 | mov ebx, 111 ; Start marker bytes
db 0x64, 0x67, 0x90 ; Start marker bytes
.innermostlooplabel:
; Loop body
; ...
jne .innermostlooplabel ; Conditional Branch Backwards to Top of Loop
mov ebx, 222 ; End marker bytes
db 0x64, 0x67, 0x90 ; End marker bytes
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Command-Line Invocation:
Invoke IACA from the command line with appropriate parameters, such as:
1 | iaca.sh -64 -arch HSW -graph insndeps.dot foo
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This will analyze the 64-bit binary foo on a Haswell CPU, generating an analysis report and a Graphviz visualization.
Output Interpretation:
The output report provides detailed information on the target code's scheduling and bottlenecks. For instance, consider the following Assembly snippet:
1 2 3 4 5 6 | .L2:
vmovaps ymm1, [rdi+rax] ;L2
vfmadd231ps ymm1, ymm2, [rsi+rax] ;L2
vmovaps [rdx+rax], ymm1 ; S1
add rax, 32 ; ADD
jne .L2 ; JMP
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By inserting markers around this code and analyzing it, IACA may report (abridged):
1 2 3 4 5 6 7 8 9 10 11 12 | Throughput Analysis Report
--------------------------
Block Throughput: 1.55 Cycles Throughput Bottleneck: FrontEnd, PORT2_AGU, PORT3_AGU
[Port Pressure Breakdown] | Instruction
--------------------------|-----------------
| | vmovaps ymm1, ymmword ptr [rdi+rax*1]
| 0.5 CP |
| 1.5 CP | vfmadd231ps ymm1, ymm2, ymmword ptr [rsi+rax*1]
| 1.5 CP | vmovaps ymmword ptr [rdx+rax*1], ymm1
| 1 CP | add rax, 0x20
| 0 CP | jnz 0xffffffffffffffec
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From this output, IACA identifies the Haswell frontend and Port 2 and 3's AGU as bottlenecks. It suggests that optimizing the store instruction to be processed by Port 7 could improve performance.
Limitations:
IACA has some limitations:
- It does not support certain instructions, which are ignored in analysis.
- It is compatible with CPUs from Nehalem onwards, excluding older models.
- Throughput mode is restricted to innermost loops, as it cannot infer branching patterns for other loops.
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