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How to make a SIMPLE C Makefile
Creating a Makefile for a Simple C Project
Problem:
- Need to create a Makefile to compile a project consisting of a single C file (a3driver.cpp) that imports a class from another location ("/user/cse232/Examples/example32.sequence.cpp").
Answer:
Creating the Makefile:
- Create a Makefile file.
-
Specify Variables:
- CC: C compiler (e.g., gcc)
- CXX: C compiler (e.g., g )
- RM: Command for removing files (e.g., rm -f)
- CPPFLAGS: Compilation flags (e.g., -g for debugging)
- LDFLAGS: Linker flags (e.g., -g for debugging)
- LDLIBS: Libraries to link (empty in this case)
-
Define Source and Object Files:
- SRCS: List of C source files
- OBJS: List of corresponding object files (generated using substitution)
-
Define Targets:
- all: Main target, defaults to building the executable
- tool: Executable name
-
Specify Dependencies:
- Specify dependencies for the executable and object files (not needed as we'll use built-in rules)
-
Use Built-in Rules:
- Makefile automatically handles compiling and linking tasks based on defined variables and target dependencies
-
Cleaning Targets:
- clean: Removes object files
- distclean: Removes all generated files
Makefile Example:
CC=gcc
CXX=g++
RM=rm -f
CPPFLAGS=-g
LDFLAGS=-g
LDLIBS=
SRCS=a3driver.cpp
OBJS=$(subst .cpp,.o,$(SRCS))
all: tool
tool: $(OBJS)
$(CXX) $(LDFLAGS) -o tool $(OBJS) $(LDLIBS)
clean:
$(RM) $(OBJS)
distclean: clean
$(RM) tool
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Running the Makefile:
- Open the terminal or command prompt.
- Navigate to the directory where the Makefile is located.
- Type "make" to build the project.
- This will create the executable file "tool" if the build is successful.
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