Why Does My Makefile Command Fail When Using Shell Expressions?

Makefile Evaluation of Expressions

When working with Makefiles, it's essential to understand how expressions are interpolated into commands. A common pitfall arises when trying to incorporate shell expressions into Makefile commands.

One such case is when working with Go tests. To skip dependencies in a vendored Go project, one might use the following command from the command line:

$ go test $(go list ./... | grep -v /vendor/)

This command successfully filters out Vendored tests. However, when attempting to include the same command in a Makefile using the following:

test:
    go test $(go list ./... | grep -v /vendor/)

.PHONY: test

The expression will not be evaluated. Instead, the command will be treated literally, leading to an error.

To resolve this issue, double-escape the dollar sign ($), as shown below:

test:
    go test $$(go list ./... | grep -v /vendor/)

.PHONY: test

By double-escaping the dollar sign, the Makefile understands that the expression should be evaluated by a shell, enabling the successful interpolation and execution of the command.

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