Can Modern x86 CPUs Really Not Atomically Store a Single Byte to Memory?

Can Modern x86 Hardware Not Store a Single Byte to Memory?

Stroustrup's statement in his book refers to the potential behavior of hypothetical hardware without a well-defined memory model. He suggests that such hardware might implement byte stores with non-atomic updates, potentially affecting neighboring bytes.

Actual Modern Hardware Behavior

However, modern hardware, including x86, does not behave in the way Stroustrup describes:

• Single-byte stores on x86 hardware are atomic and do not disturb surrounding bytes.
• Implementing byte stores with atomic RMW cycles (read-modify-write) is unnecessary and inefficient on high-performance CPUs.
• Some non-x86 CPUs may use atomic RMW cycles internally to implement byte stores, but this is not visible to external software.

Historical Context

Stroustrup's statement may have been based on the behavior of early Alpha AXP processors, which initially did not support byte load/store instructions. However, later versions of Alpha and all modern CPUs support safe and efficient byte stores.

Hardware Implementation

Modern CPUs typically use caches that store segments of memory. In a cached system:

• All byte stores within a cache line are atomic.
• The CPU fetches the entire cache line, modifies the byte, and writes the line back to memory.
• The cache controller remains in control of the line while the byte update is performed, preventing unintended changes by other cores.

Exceptions

While modern CPUs provide atomic byte stores, there may be exceptions in certain situations:

• Uncacheable memory regions may not have the same safeguards, potentially allowing non-atomic byte writes.
• I/O operations to devices may not be atomic at the byte level.

Conclusion

In practice, modern hardware supports atomic byte stores, making Stroustrup's description of potential hardware behavior less relevant to actual systems. The memory model guarantees provided by C compilers rely on the reliable behavior of modern hardware to ensure thread safety.

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