What register is tcon?
TCON: Timer control register
Register address 88H, bit addressing 8FH~88H
TF0(TF1)——Count overflow flag bit. When the counter overflows, this bit is set to 1.
TR0 (TR1) - timer operation control bit
When TR0 (TR1) = 0, stop the timer/counter operation
When TR0 (TR1) = 1, start Timer/counter operation
IE0 (IE1)——External interrupt request flag
When the CPU samples a valid interrupt request in P3.2 (P3.3), this bit is set by the hardware Set to 1. After the interrupt response is completed and the interrupt service is transferred, the hardware will automatically clear it to 0.
IT0 (IT1) - External interrupt request signal mode control bit
When IT0 (IT1) = 1 pulse mode (negative jump on the trailing edge is valid)
When IT0 ( IT1) = 0 level mode (active low level) This bit is set to 1 or cleared to 0 by software.
TF0 (TF1)——Count overflow flag bit
When the counter overflows, this bit is set to 1 by hardware. When switching to interrupt service, the hardware will automatically clear it to 0. There are two situations in which the count overflow flag bit is used: when the interrupt mode is used, it is used as the interrupt request flag bit; when the query mode is used, it is used as the query status bit.
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