What does a CPU consist of?

The composition of the CPU is: 1. The core of the CPU is divided into arithmetic units and controllers; 2. The outer core of the CPU is divided into decoders, first-level cache and second-level cache; 3. The instruction system is a The set of all instructions that the CPU can process is the fundamental attribute of a CPU.

The composition of cpu is:

##1. The core of the CPU

Structurally speaking, the CPU core is divided into two parts: arithmetic unit and controller.

(1)Arithmetic unit

1. Arithmetic and Logic Unit ALU

ALU mainly completes fixed-point arithmetic operations (addition, subtraction, multiplication and division) on binary data ), logical operations (AND or NOT XOR) and shift operations. In some CPUs, there are shifters specifically designed to handle shift operations.

Usually ALU consists of two input terminals and one output terminal. Integer units are sometimes called IEU (Integer Execution Unit). What we usually say "CPU is XX bits" refers to the number of data bits that the ALU can process.

2. Floating Point Unit FPU (Floating Point Unit)

FPU is mainly responsible for floating point operations and high-precision integer operations. Some FPUs also have the function of vector operations, and others have specialized vector processing units.

3. General-purpose register group

The general-purpose register group is a group of fastest memories used to store operands and intermediate results participating in operations.

Regarding the shortcoming that the x86 instruction set only supports 8 general-purpose registers, Intel's latest CPU adopts a technology called "register renaming". This technology allows the x86 CPU's registers to break through the limit of 8 registers and reach 32 or more.

4. Special registers

Special registers are usually status registers that cannot be changed by the program and are controlled by the CPU itself to indicate a certain status.

(2) Controller

The calculator can only complete operations, while the controller is used to control the work of the entire CPU.

1. Instruction controller

The instruction controller is a very important part of the controller. It must complete operations such as fetching instructions and analyzing instructions, and then hands them to the execution unit (ALU or FPU) to execute, and at the same time form the address of the next instruction.

2. Timing controller

The function of the timing controller is to provide control signals for each instruction in time sequence. The timing controller includes a clock generator and a frequency multiplication definition unit. The clock generator emits a very stable pulse signal from a quartz crystal oscillator, which is the main frequency of the CPU. The frequency multiplication definition unit defines the CPU main frequency as the memory frequency ( several times the bus frequency).

3. Bus controller

The bus controller is mainly used to control the internal and external buses of the CPU, including address bus, data bus, control bus, etc.

4. Interrupt controller

The interrupt controller is used to control various interrupt requests, queue the interrupt requests according to their priority, and hand them over to the CPU for processing one by one.

2. The outer core of the CPU

1. Decoder (Decode Unit)

This is a unique device of x86CPU. Its function is to Variable-length x86 instructions are converted into fixed-length instructions and handed over to the kernel for processing. Decoding is divided into hardware decoding and micro decoding. For simple x86 instructions, only hardware decoding is enough, which is faster. However, when encountering complex x86 instructions, you need to perform micro decoding and divide it into several simple instructions, which is slower and faster. Very complicated. Fortunately, these complex instructions are rarely used.

2. Level 1 cache and level 2 cache (Cache)

The level 1 cache and level 2 cache are created to alleviate the conflict between faster CPU and slower memory. , and the cache is usually integrated in the CPU core, while the second-level cache runs faster than the memory in the form of OnDie or OnBoard. For some tasks with large data exchange volume, the CPU Cache is particularly important.

3. Instruction system

To talk about CPU, we also need to understand the instruction system. The instruction system refers to the set of all instructions that a CPU can process. It is the fundamental attribute of a CPU, because the instruction system determines what kind of programs a CPU can run. The CPUs we often talk about are all X86 series and compatible CPUs. The so-called X86 instruction set was specially developed by the American Intel Corporation for its first 16-bit CPU (i8086). Although with the continuous development of CPU technology, Intel has successively developed newer i80386 and i80486 until today's Pentium4 series, but in order to ensure that the computer can continue to run various applications developed in the past to protect and inherit rich software resources (such as the Windows series), all CPUs produced by Intel continue to use X86 Instruction Set. In addition to Intel, manufacturers such as AMD and Cyrix have also successively produced CPUs that can use the It is Intel's CPU compatible product.

4. Brief analysis of main CPU technologies

1. Pipeline technology

The pipeline was first used by Intel in the 486 chip. The assembly line works like an assembly line in industrial production. In the CPU, an instruction processing pipeline is composed of 5 to 6 circuit units with different functions, and then an X86 instruction is divided into 5 to 6 steps and then executed by these circuit units respectively, so that one instruction can be completed in one CPU clock cycle. , thereby improving the computing speed of the CPU.

2. Super pipeline and superscalar technology

Super pipeline refers to the pipeline inside some CPUs exceeding the usual 5 to 6 steps. For example, the pipeline of Intel Pentium 4 is as long as 20 steps. . The more steps (stages) the pipeline is designed to complete, the faster it can complete an instruction, so it can adapt to CPUs with higher operating frequencies. Superscalar means that there is more than one pipeline in the CPU and more than one instruction can be completed per clock cycle. This design is called superscalar technology.

3. Out-of-order execution technology

Out-of-order execution means that the CPU adopts a method that allows multiple instructions to be sent to each corresponding circuit separately without following the order specified by the program. Unit processing technology. For example, if there are 7 instructions in a certain section of the program, the CPU will immediately send the instructions that can be executed in advance to the corresponding circuit for execution based on the idle status of each unit circuit and the specific situation of whether each instruction can be executed in advance. Of course, after each unit executes instructions out of the specified order, the corresponding circuit must re-arrange the operation results in the order of instructions specified by the original program before returning to the program. This kind of operation method in which instructions are separated and executed out of order is called out-of-order execution (also called out-of-order execution) technology. The purpose of using out-of-order execution technology is to make the CPU's internal circuits operate at full capacity and accordingly increase the speed of the CPU's running programs.

4. Branch prediction and speculative execution technology

Branch prediction and speculative execution are the main contents of CPU dynamic execution technology. Dynamic execution is currently the One of the advanced technologies mainly used by CPU. The main purpose of using branch prediction and dynamic execution is to increase the computing speed of the CPU. Speculative execution is based on branch prediction. The processing performed after the branch prediction program branches is also speculative execution.

5. Instruction special expansion technology

Since the most Starting with a simple computer, a sequence of instructions can obtain operands and perform calculations on them. On most computers, these instructions can only perform one calculation at a time. To complete some parallel operations, multiple calculations must be performed continuously. This type of computer uses a "Single Instruction Single Data" (SISD) processor. When introducing CPU performance, "extended instructions" or "special extensions" are often mentioned, which all refer to whether the CPU has instruction extensions to the X86 instruction set. The first extension instructions to appear were Intel Corporation's "MMX", then "SSE" in Pentium III, and now the SSE2 instruction set in Pentium 4.

5. CPU architecture and packaging method

(1) CPU architecture

The CPU architecture is determined according to the type and specification of the CPU’s installation socket of. Currently commonly used CPUs can be divided into two architectures: Socket x and Slot x according to their installation socket specifications.

Taking the Intel processor as an example, the Socket architecture CPU is divided into three types: Socket 370, Socket 423 and Socket 478, which respectively correspond to the Intel PIII/Celeron processor, P4 Socket 423 processor and P4 Socket 478 processing. device. Slot x architecture CPUs can be divided into two types: Slot 1 and Slot 2, which are installed in slots with corresponding specifications. Slot 1 is the architecture adopted by early Intel PII, PIII and Celeron processors. Slot 2 is a larger slot specially used to install Xeon in the PII and PIII series. Xeon is a CPU designed for workgroup servers.

(2) CPU packaging method

The so-called packaging refers to the shell used to install the semiconductor integrated circuit chip, which is connected to the pins of the packaging shell through the contacts on the chip with wires. These pins The pins are connected to other devices through slots on the printed circuit board. It plays a role in installing, fixing, sealing, protecting chips and enhancing electric and thermal performance.

The packaging method of the CPU depends on the CPU installation form. Usually, the CPU installed in the Socket socket is packaged in the form of PGA (Grid Array), while the CPU installed in the Slot X slot is all packaged in SEC (Single Side). package in the form of a connector box).

1. PGA (Pin Grid Arrax) pin grid array package

The current packaging method of CPU is basically PGA packaging, with a multi-layer square array of pins surrounding the bottom of the chip. Each square array of pins is arranged at a certain distance along the periphery of the chip. Its pins look like needles and are connected to the circuit board using plug-ins. When installing, insert the chip into the dedicated PGA socket. The PGA package has the advantages of more convenient plugging and unplugging operations and high reliability. The disadvantage is that it consumes more power. PGA also derives a variety of packaging methods. The earliest PGA package is suitable for Intel Pentium, Intel Pentium PRO and Cxrix/IBM 6x86 processors; CPGA (Ceramic Pin Grid Arrax, ceramic pin grid array) package is suitable for Intel Pentium MMX , AMD K6, AMD K6-2, AMD K6 III, VIA Cxrix III processor; PPGA (Plastic Pin Grid Arrax, plastic pin matrix) package, suitable for Intel Celeron processor (Socket 370); FC-PGA (Flip Chip Chip Pin Grid Arrax, inverted chip pin grid array) package, suitable for Coppermine series Pentium III, Celeron II and Pentium4 processors.

2. SEC (Single Side Connector Box) Package

The Slot X architecture CPU no longer uses ceramic packaging, but uses a printed circuit board with a metal shell. The printed circuit board The circuit board integrates the processor components. The plastic enclosure of the SEC card is called SEC (Single Edgecontact Cartridge). This SEC card is designed to be inserted into Slot X (about the size of an ISA slot) slot. All Slot X motherboards have a fixing mechanism consisting of two plastic brackets, and an SEC card can be inserted into the Slot X slot from between the two plastic brackets.

Among them, Intel Celeron processor (Slot 1) adopts (SEPP) single-edge processor package; Intel's Pentium II adopts SECC (Single Edge Contact Connector, single-edge contact connection) package; Intel's Pentium III It is packaged in SECC2.

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