What does a computer's memory unit consist of?

The computer's memory unit consists of two parts: memory and sequential access control. Memory units are divided into latches and flip-flops according to the level sensitivity and edge sensitivity of the clock; according to the type of input terminal, they can be divided into SR type, JK type, D type, and T type.

The memory unit is the basic component of the memory. The memory unit is composed of internal storage (memory) and sequential access control.

Category

1. One of the classifications

Memory units are divided into latches and flip-flops according to the level sensitivity and edge sensitivity of the clock. The register can be two arrays composed of these two components respectively. They are introduced below.

(1) Latch - A level-sensitive memory unit is called a latch. For example, the TTL device 7475 relies on the high or low level of the input clock to achieve gating.

(2) Flip-flop - an edge-sensitive memory unit is called a flip-flop. For example, the TTL device 7474 is triggered by the rising or falling edge of the input clock.

In many materials, the internal storage value is transparently transmitted and set by the input data, which is called a latch. Flip-flops, especially master-slave latches, mean that the reading of the input value and the change of the output value are two opaque independent events. This opacity between input and output also leads to the emergence of the role of the clock trigger edge. Note that the different definitions of latches and flip-flops reflect different viewing perspectives, but they are still related. Change back to the more popular definition above.

(3) Register (Register) - generally refers to an array composed of multiple flip-flops, used to store multi-bit data; a latch array, such as a data bus, may also be used. Note that in some cases it also refers to a single flip-flop or latch.

2. Classification 2

Memory units can also be classified according to the type of input terminal.

(1) SR type - the set reset type can be subdivided into two types: SR and SR. Refer to Figure 1.

At this time, based on the state of the output Q terminal, the memory unit state is either set by 0 at the S input terminal; or reset by 0 at the R input terminal: If S, R If both are 1, the state is maintained; however, S and R cannot be 0 at the same time. For the SR type in the same narrow sense, the situation is opposite.

(2) JK type - similar to SR type, but the J input terminal and the K input terminal can be 1 (state flip) or 0 (state maintenance) at the same time. JK type can be used to form other types of memory units.

(3) D type - D input terminal provides data (Data). Some information says that D stands for delay. When a clock event occurs, its output Q terminal value is transparently determined by the input D value.

(4) T type - You can connect the Q of the D type to D, and use T as the input of the clock

terminal. At this time, the Q output will be the frequency divided by two of the T clock signal. For this T type, a frequency division enable control terminal can also be added.

For memory units, the most important thing is still to store the correct data at the right location and at the right moment. In order for the memory unit to work reliably, two rated parameters used to characterize the relationship between data and clock constraints - data setup time and hold time must be met. For memory unit circuits that are triggered by the rising edge of the clock, the minimum stable period of data before the rising edge of the clock (some documents also take the midpoint of the rising edge) is called setup (sp), and the period after that is called hold (hp). The cumulative delay factor after cascading logic gates often destroys the rated requirements of the memory unit sp and hp, thereby limiting the maximum speed of the entire system. This is often something that needs to be paid close attention to when analyzing waveforms.

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