Is the jk flip-flop rising edge or falling edge?

Not all Jk flip-flops are valid on the falling edge. Whether it is valid on the falling edge or on the rising edge is related to the internal structure of the flip-flop. The falling rising edge is valid means that the state of the flip-flop may change only when the clock signal transitions from high level to low level.

The operating environment of this tutorial: Windows 7 system, Dell G3 computer.

It is triggered by the falling edge. There is a small circle on the CP control signal to indicate that the falling edge is valid.

The rising edge is valid means that the state of the flip-flop can change only when the clock signal transitions from low level to high level. Similarly, the falling rising edge is valid means that the clock signal is at The state of the flip-flop may change only when it transitions from high level to low level.

In addition, not all Jk flip-flops are valid on the falling edge, and not all D flip-flops are valid on the rising edge. There is no such corresponding relationship. As for whether it is valid on the falling edge or on the rising edge, It has to do with the internal structure of the trigger.

JK flip-flop has set 0, set 1, hold and flip functions. Among various types of integrated flip-flops, JK flip-flop has the most complete functions. In practical applications, it not only has strong versatility, but also can flexibly convert other types of flip-flops. D flip-flops and T flip-flops can be constructed from JK flip-flops.

The structure of the JK flip-flop is similar to the RS flip-flop, the most basic flip-flop. The difference is that the RS flip-flop does not allow R and S to be 1 at the same time, while the JK flip-flop allows J and K to be 1 at the same time. When J and K become 1 at the same time, the value state of the output will be reversed. In other words, if it was originally 0, it becomes 1; if it was originally 1, it becomes 0.

Extended information

JK trigger working characteristics

Establishment time: means that the input signal should precede The time when the CP signal arrives is represented by tset. It can be seen from Figure 7.5.5 that the J and K signals only need to arrive no later than the CP signal, so tset=0.

Hold time: In order to ensure reliable flip-flop of the flip-flop, the input signal needs to be held for a certain period of time. The holding time is expressed as tH. If the status of J and K is required to remain unchanged during CP=1, and the time when CP=1 is tWH, then it should be satisfied: tH≥tWH.

Transmission delay time: If the period from the falling edge of CP to the stable establishment of a new state at the output is defined as the transmission time, then: tPLH=3tpd tPHL=4tpd Maximum clock frequency: Because the main The slave flip-flops are composed of two synchronous RS flip-flops, so the dynamic characteristics of the synchronous RS flip-flops can be known.

To ensure the reliable flip of the main flip-flop, the duration tWH of CP high level should be greater than 3tpd. In the same way, in order to ensure that the slave flip-flop can flip reliably, the duration tWL of CP low level should also be greater than 3tpd. Therefore, the minimum period of the clock signal is: Tc(min)≥6tpd and the maximum clock frequency fc(max)≤1/6tpd.

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