Home Technology peripherals It Industry HBM4 memory is under development and will use a wider 2048 bit interface

HBM4 memory is under development and will use a wider 2048 bit interface

Oct 15, 2023 pm 06:13 PM
Memory Samsung Micron sk hynix hbm4

Samsung official news shows that HBM memory for high-performance computing (HPC) has made new progress. The 9.8Gbps HBM3E product has begun sampling to customers, while HBM4 memory is expected to launch in 2025. Although there are no official specifications for HBM4 yet, TSMC revealed at the 2023 OIP Forum that some are in the works standards. TSMC stated that the interface bit width of HBM4 memory will double in the future to 2048 bits

HBM4 内存正在开发中,将采用更宽的 2048 bit 接口
It is worth mentioning that for various technical reasons , they also hope to achieve this goal without increasing the footprint of the HBM memory stack, which will also double the interconnect density of the next generation HBM memory without further increasing the clock speed.

According to the plan, this will enable HBM4 to achieve major breakthroughs at multiple technical levels

In terms of DRAM stacking, a 2048bit memory interface requires a significant increase in the number of through-silicon vias. At the same time, the external chip interface will need to reduce the bump pitch to less than 55 microns and significantly increase the number of micro-bumps (Note from this site: HBM3 currently has approximately 3982 micro-bumps).

HBM4 内存正在开发中,将采用更宽的 2048 bit 接口
In addition, HBM4 will adopt a 16-Hi stacking mode, which stacks 16 memory chips in one module, thus increasing the technical complexity ( Although from a technical perspective, HBM3 also supports 16-Hi stacking, no manufacturer has actually adopted this so far)

All these new metrics in turn require chip manufacturers, memory manufacturers and Chip packaging companies are taking a closer collaborative approach to ensure everything runs smoothly.

At TSMC OIP 2023 conference in Amsterdam, Dan Kochpatcharin, head of design infrastructure management at TSMC, said: "Because they are not doubling the speed, but [ interface] pins [with HBM4] are doubled. That's why we're working hard to make sure that we work with all three partners to qualify their HBM4 [that can pass through our advanced packaging] and make sure that the RDL or the mediator or both Any content in between can support the layout and speed of HBM4. Therefore, we are maintaining cooperation with Samsung, SK Hynix and Micron."

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