According to news from this site on November 6, high-performance RISC-V CPU design company Ventana and Imagination jointly developed heterogeneous CPU-GPU SoC. The two companies will display their simulation models at the RISC-V Summit next week.
According to reports, both companies are major members of the RISC-V International and RISC-V Software Ecosystem (RISE) projects, and both Is a strong advocate of open architecture.
Ventana Micro Systems was founded in 2018 and its first product is the Veyron V1, launched at the RISC-V Summit in December 2022. Ventana will launch Veyron V2 next week, and this joint innovation is expected to be around this goal.
It is said that the main change in V2 compared to V1 is that RISC-V ISA will have most of the necessary features to compete with x86/Arm, such as standards Vector extensions and IOMMU specifications. It will include:
Hypervisor extension
Type 1 and Type 2 hypervisors; nested virtualization
Advanced Interrupt Architecture (AIA)
Includes native MSI handling and interrupt virtualization
Debugging can be divided into external debugging and automatic Managed debugging, memory tracking is also a way of debugging
The content that needs to be rewritten is: rich performance events and performance counters
This site query found that the RVA23 feature set includes UCIe chip interface, 40% performance improvement, 512b vector unit AI matrix expansion, server-level IOMMU and RISE software compatibility platform , and Domain Specific Acceleration (DSA).
Related reading:
Imagination announced its upgrade to RISC-V premium membership, indicating that all its GPUs are compatible with RISC-V SoC
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